File: ../../Sources/A21_compute_map.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: A21_compute_map - Behavioral
4: --
5: -- Description: Code segment A.21
6: -- Computation of map for Errval mapping
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a21_compute_map is
16: generic (
17: K_WIDTH : natural := CO_K_WIDTH_STD;
18: N_WIDTH : natural := CO_NQ_WIDTH_STD;
19: ERROR_WIDTH : natural := CO_ERROR_VALUE_WIDTH_STD
20: );
21: port (
22: iK : in unsigned (K_WIDTH - 1 downto 0);
23: iErrval : in signed (ERROR_WIDTH - 1 downto 0);
24: iNn : in unsigned (N_WIDTH - 1 downto 0);
25: iNq : in unsigned (N_WIDTH - 1 downto 0);
26: oMap : out std_logic
27: );
28: end entity a21_compute_map;
29:
30: architecture behavioral of a21_compute_map is
31:
32: signal sNnExt : unsigned (N_WIDTH downto 0);
33: signal sNqExt : unsigned (N_WIDTH downto 0);
34:
35: begin
36:
37: sNnExt <= resize(iNn, sNnExt'length);
38: sNqExt <= resize(iNq, sNqExt'length);
39:
40: p_compute_map : process (iK, iErrval, sNnExt, sNqExt) is
41:
42: variable vMap : std_logic;
43:
44: begin
45:
46: if ((iK = 0) and (iErrval > 0) and (shift_left(sNnExt, 1) < sNqExt)) then
47: vMap := '1';
48: elsif ((iErrval < 0) and (shift_left(sNnExt, 1) >= sNqExt)) then
49: vMap := '1';
50: elsif ((iErrval < 0) and (iK /= 0)) then
51: vMap := '1';
52: else
53: vMap := '0';
54: end if;
55:
56: oMap <= vMap;
57:
58: end process p_compute_map;
59:
60: end architecture behavioral;