File: ../../Sources/A4_1_quant_gradient_merging.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: quant_gradient_merging - Behavioral
4: --
5: -- Description: Code segment A.4.1
6: -- Text only, described on section A.3.4
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a4_1_quant_gradient_merging is
16: port (
17: iQ1 : in signed(3 downto 0);
18: iQ2 : in signed(3 downto 0);
19: iQ3 : in signed(3 downto 0);
20: oQ1 : out signed(3 downto 0);
21: oQ2 : out signed(3 downto 0);
22: oQ3 : out signed(3 downto 0);
23: oSign : out std_logic
24: );
25: end entity a4_1_quant_gradient_merging;
26:
27: architecture behavioral of a4_1_quant_gradient_merging is
28:
29: signal sSign : std_logic;
30:
31: begin
32:
33: -- Sign of first non-zero (1 if negative)
34: sSign <= CO_SIGN_NEG when iQ1 < 0 else
35: CO_SIGN_NEG when (iQ1 = 0 and iQ2 < 0) else
36: CO_SIGN_NEG when (iQ1 = 0 and iQ2 = 0 and iQ3 < 0) else
37: CO_SIGN_POS;
38:
39: -- Flip quantized values if sign is negative
40: oQ1 <= - iQ1 when sSign = CO_SIGN_NEG else
41: iQ1;
42: oQ2 <= - iQ2 when sSign = CO_SIGN_NEG else
43: iQ2;
44: oQ3 <= - iQ3 when sSign = CO_SIGN_NEG else
45: iQ3;
46:
47: oSign <= sSign;
48:
49: end architecture behavioral;