File: ../../Sources/A5_edge_detecting_predictor.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: edge_detecting_predictor - Behavioral
4: --
5: -- Description: Code segment A.5
6: -- Edge-detecting predictor
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a5_edge_detecting_predictor is
16: generic (
17: BITNESS : natural range 8 to 16 := CO_BITNESS_STD
18: );
19: port (
20: iA : in unsigned (BITNESS - 1 downto 0);
21: iB : in unsigned (BITNESS - 1 downto 0);
22: iC : in unsigned (BITNESS - 1 downto 0);
23: oPx : out unsigned (BITNESS - 1 downto 0)
24: );
25: end entity a5_edge_detecting_predictor;
26:
27: architecture behavioral of a5_edge_detecting_predictor is
28:
29: begin
30:
31: oPx <= math_min(iA, iB) when iC >= math_max(iA, iB) else
32: math_max(iA, iB) when iC <= math_min(iA, iB) else
33: iA + iB - iC;
34:
35: end architecture behavioral;