File: ../../Sources/A12_variables_update.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: A12_variables_update - Behavioral
4: --
5: -- Assumptions:
6: -- B_WIDTH >= ERROR_WIDTH
7: -- A_WIDTH >= ERROR_WIDTH
8: --
9: ----------------------------------------------------------------------------------
10:
11: library ieee;
12: use ieee.std_logic_1164.all;
13: use ieee.numeric_std.all;
14: use work.openjls_pkg.all;
15:
16: entity a12_variables_update is
17: generic (
18: ERROR_WIDTH : natural := CO_ERROR_VALUE_WIDTH_STD;
19: A_WIDTH : natural := CO_AQ_WIDTH_STD;
20: B_WIDTH : natural := CO_BQ_WIDTH_STD;
21: N_WIDTH : natural := CO_NQ_WIDTH_STD;
22: RESET : natural := CO_RESET_STD
23: );
24: port (
25: iErrorVal : in signed (ERROR_WIDTH - 1 downto 0);
26: iAq : in unsigned (A_WIDTH - 1 downto 0);
27: iBq : in signed (B_WIDTH - 1 downto 0);
28: iNq : in unsigned (N_WIDTH - 1 downto 0);
29:
30: oAq : out unsigned (A_WIDTH - 1 downto 0);
31: oBq : out signed (B_WIDTH - 1 downto 0);
32: oNq : out unsigned (N_WIDTH - 1 downto 0)
33: );
34: end entity a12_variables_update;
35:
36: architecture rtl of a12_variables_update is
37:
38: signal sDoRescale : std_logic;
39: signal sErrorAbsExtend : unsigned(A_WIDTH - 1 downto 0);
40: signal sAqNew : unsigned(A_WIDTH - 1 downto 0);
41: signal sBqNew : signed (B_WIDTH - 1 downto 0);
42: signal sNqNew : unsigned(N_WIDTH - 1 downto 0);
43: signal sARescale : unsigned(A_WIDTH - 1 downto 0);
44: signal sBRescale : signed (B_WIDTH - 1 downto 0);
45: signal sNRescale : unsigned(N_WIDTH - 1 downto 0);
46:
47: begin
48:
49: sDoRescale <= '1' when (iNq = to_unsigned(RESET, iNq'length)) else
50: '0';
51:
52: sErrorAbsExtend <= resize(unsigned(abs(iErrorVal)), A_WIDTH);
53:
54: sAqNew <= iAq + sErrorAbsExtend;
55: sBqNew <= iBq + resize(iErrorVal, B_WIDTH);
56: sNqNew <= iNq + 1;
57:
58: -- Rescale: halve A & B; N sequencing: (N>>1) + 1 (per T.87)
59: sARescale <= shift_right(sAqNew, 1);
60: sBRescale <= shift_right(sBqNew, 1); -- arithmetic >> 1 => floor for negatives
61: sNRescale <= shift_right(iNq, 1) + 1;
62:
63: oAq <= sARescale when sDoRescale = '1' else
64: sAqNew;
65: oBq <= sBRescale when sDoRescale = '1' else
66: sBqNew;
67: oNq <= sNRescale when sDoRescale = '1' else
68: sNqNew;
69:
70: end architecture rtl;