File: ../../Sources/A4_2_Q_mapping.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: A4_2_Q_mapping - Behavioral
4: --
5: -- Description: Written requirement A.4.2 - Merge quantized vector into Q
6: --
7: ----------------------------------------------------------------------------------
8:
9: library ieee;
10: use ieee.std_logic_1164.all;
11: use ieee.numeric_std.all;
12:
13: entity a4_2_q_mapping is
14: port (
15: iQ1 : in signed(3 downto 0); -- [0, 4]
16: iQ2 : in signed(3 downto 0); -- [-4, 4]
17: iQ3 : in signed(3 downto 0); -- [-4, 4]
18: oQ : out unsigned(8 downto 0) -- [0..364]
19: );
20: end entity a4_2_q_mapping;
21:
22: architecture behavioral of a4_2_q_mapping is
23:
24: -- Q = 81*Q1 + 9*Q2 + Q3 (Mert, 2018)
25: signal sQ1 : unsigned(2 downto 0);
26: signal s81 : unsigned(8 downto 0); -- 81*Q1, [0..324]
27: signal s9 : signed(7 downto 0); -- 9*Q2, [-72..72]
28:
29: begin
30:
31: sQ1 <= unsigned(iQ1(2 downto 0)); -- Q1 is in range [0..4]
32:
33: s81 <= shift_left(resize(sQ1, 9), 6)
34: or shift_left(resize(sQ1, 9), 4)
35: or resize(sQ1, 9);
36:
37: s9 <= shift_left(resize(iQ2, 8), 3)
38: + resize(iQ2, 8);
39:
40: oQ <= resize(unsigned(signed('0' & s81) + s9 + iQ3), 9);
41:
42: end architecture behavioral;