File: ../../Sources/A13_update_bias.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: A13_update_bias - Behavioral
4: --
5: -- Assumptions:
6: -- B_WIDTH >= N_WIDTH
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a13_update_bias is
16: generic (
17: B_WIDTH : natural := CO_BQ_WIDTH_STD;
18: N_WIDTH : natural := CO_NQ_WIDTH_STD;
19: C_WIDTH : natural := CO_CQ_WIDTH;
20: MIN_C : integer := CO_MIN_CQ;
21: MAX_C : integer := CO_MAX_CQ
22: );
23: port (
24: iBq : in signed (B_WIDTH - 1 downto 0);
25: iNq : in unsigned (N_WIDTH - 1 downto 0);
26: iCq : in signed (C_WIDTH - 1 downto 0);
27: oBq : out signed (B_WIDTH - 1 downto 0);
28: oCq : out signed (C_WIDTH - 1 downto 0)
29: );
30: end entity a13_update_bias;
31:
32: architecture rtl of a13_update_bias is
33:
34: signal sIsBNegBranch : std_logic;
35: signal sIsBPosBranch : std_logic;
36: signal sNeedNegClp : std_logic;
37: signal sNeedPosClp : std_logic;
38: signal sNqSig : signed(iBq'range); -- signed and extended Nq
39: signal sBNegFinal : signed(iBq'range);
40: signal sBPosFinal : signed(iBq'range);
41: signal sCDec : signed(iCq'range);
42: signal sCInc : signed(iCq'range);
43:
44: begin
45:
46: sNqSig <= signed(resize(iNq, B_WIDTH));
47:
48: sIsBNegBranch <= '1' when iBq <= - sNqSig else
49: '0';
50: sIsBPosBranch <= '1' when iBq > 0 else
51: '0';
52:
53: sCDec <= iCq - 1 when iCq > MIN_C else
54: iCq;
55: sCInc <= iCq + 1 when iCq < MAX_C else
56: iCq;
57:
58: sNeedNegClp <= '1' when iBq + sNqSig <= - sNqSig else
59: '0';
60: sNeedPosClp <= '1' when iBq - sNqSig > 0 else
61: '0';
62:
63: sBNegFinal <= - sNqSig + 1 when sNeedNegClp = '1' else
64: iBq + sNqSig;
65: sBPosFinal <= to_signed(0, sBPosFinal'length) when sNeedPosClp = '1' else
66: iBq - sNqSig;
67:
68: oBq <= sBNegFinal when sIsBNegBranch = '1' else
69: sBPosFinal when sIsBPosBranch = '1' else
70: iBq;
71:
72: oCq <= sCDec when sIsBNegBranch = '1' else
73: sCInc when sIsBPosBranch = '1' else
74: iCq;
75:
76: end architecture rtl;