File: ../../Sources/A18_run_interruption_prediction_error.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: A18_run_interruption_prediction_error - Behavioral
4: --
5: -- Description: Code segment A.18
6: -- Prediction error for a run interruption sample
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a18_run_interruption_prediction_error is
16: generic (
17: BITNESS : natural range 8 to 16 := CO_BITNESS_STD
18: );
19: port (
20: iRItype : in std_logic;
21: iRa : in unsigned (BITNESS - 1 downto 0);
22: iRb : in unsigned (BITNESS - 1 downto 0);
23: iIx : in unsigned (BITNESS - 1 downto 0);
24: oErrval : out signed (BITNESS downto 0)
25: );
26: end entity a18_run_interruption_prediction_error;
27:
28: architecture behavioral of a18_run_interruption_prediction_error is
29:
30: signal sPx : unsigned (BITNESS - 1 downto 0);
31:
32: begin
33:
34: sPx <= iRa when iRItype = '1' else
35: iRb;
36:
37: oErrval <= signed('0' & iIx) - signed('0' & sPx);
38:
39: end architecture behavioral;