File: ../../Sources/A6_prediction_correction.vhd
0: ----------------------------------------------------------------------------------
1: -- Engineer: Vitor Mendes Camilo
2: --
3: -- Module Name: prediction_correction - Behavioral
4: --
5: -- Description: Code segment A.6
6: -- Prediction correction from the bias
7: --
8: ----------------------------------------------------------------------------------
9:
10: library ieee;
11: use ieee.std_logic_1164.all;
12: use ieee.numeric_std.all;
13: use work.openjls_pkg.all;
14:
15: entity a6_prediction_correction is
16: generic (
17: BITNESS : natural := CO_BITNESS_STD;
18: MAX_VAL : natural := CO_MAX_VAL_STD
19: );
20: port (
21: iPx : in unsigned (BITNESS - 1 downto 0);
22: iSign : in std_logic;
23: iCq : in signed (CO_CQ_WIDTH - 1 downto 0);
24: oPx : out unsigned (BITNESS - 1 downto 0)
25: );
26: end entity a6_prediction_correction;
27:
28: architecture behavioral of a6_prediction_correction is
29:
30: constant EXT_WIDTH : natural := BITNESS + 2;
31: constant ZERO_S : signed(EXT_WIDTH - 1 downto 0) := (others => '0');
32: constant MAX_S : signed(EXT_WIDTH - 1 downto 0) := to_signed(MAX_VAL, EXT_WIDTH);
33:
34: signal sPxPlusCq : signed (EXT_WIDTH - 1 downto 0);
35: signal sPxMinusCq : signed (EXT_WIDTH - 1 downto 0);
36:
37: -- Precomputed saturated results (vector-select is shallow)
38: signal sAddSat : unsigned (BITNESS - 1 downto 0);
39: signal sSubSat : unsigned (BITNESS - 1 downto 0);
40:
41: begin
42:
43: -- Align widths explicitly for portable, predictable arithmetic
44: sPxPlusCq <= resize(signed('0' & iPx), EXT_WIDTH) + resize(iCq, EXT_WIDTH);
45: sPxMinusCq <= resize(signed('0' & iPx), EXT_WIDTH) - resize(iCq, EXT_WIDTH);
46:
47: -- Saturate add/sub results in parallel
48: sAddSat <= (others => '0') when (sPxPlusCq < ZERO_S) else
49: TO_UNSIGNED(MAX_VAL, BITNESS) when (sPxPlusCq > MAX_S) else
50: unsigned(sPxPlusCq(BITNESS - 1 downto 0));
51: sSubSat <= (others => '0') when (sPxMinusCq < ZERO_S) else
52: TO_UNSIGNED(MAX_VAL, BITNESS) when (sPxMinusCq > MAX_S) else
53: unsigned(sPxMinusCq(BITNESS - 1 downto 0));
54:
55: -- Final 2:1 mux by sign
56: oPx <= sAddSat when iSign = CO_SIGN_POS else
57: sSubSat;
58:
59: end architecture behavioral;