Xilinx Requirement Results

Requirement	TestName	Status	Requirements		Checks			Alert Counts			Disabled Alert Counts
			Goal	Passed	Total	Passed	Failed	Failures	Errors	Warnings	Failures	Errors	Warnings
OJLS.AxiAbortReencode	Merged	PASSED	57	171	174	174	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
OJLS.AxiApplyReconfig	Merged	PASSED	57	171	174	174	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	57	58	58	58	0	0	0	0	0	0	0
OJLS.AxiLiteRegMap	Merged	PASSED	16	48	51	51	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	16	17	17	17	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	16	17	17	17	0	0	0	0	0	0	0
	tb_openjls_axis_regs_osvvm	PASSED	16	17	17	17	0	0	0	0	0	0	0
OJLS.AxiStreamTransparent	Merged	PASSED	315	885	900	900	0	0	0	0	0	0	0
	tb_openjls_axis_osvvm	PASSED	285	290	290	290	0	0	0	0	0	0	0
	tb_openjls_axis_osvvm	PASSED	285	290	290	290	0	0	0	0	0	0	0
	tb_openjls_axis_osvvm	PASSED	315	320	320	320	0	0	0	0	0	0	0