Covered statements:
Variable assignment statement on line 150:
150: vNew := vcur;
Count: 27
Threshold: 1
If statement on lines 152 to 154:
152: if (vwstrb(0) = '1') then
153: vNew(7 downto 0) := unsigned(vwdata(7 downto 0));
154: end if;
Count: 27
Threshold: 1
Variable assignment statement on line 153:
153: vNew(7 downto 0) := unsigned(vwdata(7 downto 0));
Count: 24
Threshold: 1
If statement on lines 156 to 158:
156: if (vwstrb(1) = '1') then
157: vNew(15 downto 8) := unsigned(vwdata(15 downto 8));
158: end if;
Count: 27
Threshold: 1
Variable assignment statement on line 157:
157: vNew(15 downto 8) := unsigned(vwdata(15 downto 8));
Count: 24
Threshold: 1
If statement on lines 160 to 162:
160: if (vNew < vmindim or vNew > vmaxdim) then
161: vNew := to_unsigned(vmaxdim, vNew'length);
162: end if;
Count: 27
Threshold: 1
Variable assignment statement on line 161:
161: vNew := to_unsigned(vmaxdim, vNew'length);
Count: 6
Threshold: 1
Sequential statement on line 164:
164: return vNew;
Count: 27
Threshold: 1
If statement on lines 177 to 178:
177: sWrHandshake <= '1' when s_axi_ctrl_awvalid = '1' and s_axi_ctrl_wvalid = '1' and sBValid = '0' else
178: '0';
Count: 135
Threshold: 1
Signal assignment statement on line 177:
177: sWrHandshake <= '1' when s_axi_ctrl_awvalid = '1' and s_axi_ctrl_wvalid = '1' and sBValid = '0' else
Count: 36
Threshold: 1
Signal assignment statement on line 178:
178: '0';
Count: 99
Threshold: 1
Signal assignment statement on line 180:
180: s_axi_ctrl_awready <= sWrHandshake;
Count: 78
Threshold: 1
Signal assignment statement on line 181:
181: s_axi_ctrl_wready <= sWrHandshake;
Count: 78
Threshold: 1
Signal assignment statement on line 182:
182: s_axi_ctrl_bresp <= "00"; -- OKAY; RO/unmapped writes are silently dropped
Count: 3
Threshold: 1
Signal assignment statement on line 183:
183: s_axi_ctrl_bvalid <= sBValid;
Count: 78
Threshold: 1
If statement on lines 191 to 240:
191: if rising_edge(aclk) then
192: if (aresetn = '0') then
...
239: end if;
240: end if;
Count: 1156
Threshold: 1
If statement on lines 192 to 239:
192: if (aresetn = '0') then
193: sBValid <= '0';
...
238: end if;
239: end if;
Count: 578
Threshold: 1
Signal assignment statement on line 193:
193: sBValid <= '0';
Count: 24
Threshold: 1
Signal assignment statement on line 194:
194: sWidth <= to_unsigned(MAX_IMAGE_WIDTH, sWidth'length);
Count: 24
Threshold: 1
Signal assignment statement on line 195:
195: sHeight <= to_unsigned(MAX_IMAGE_HEIGHT, sHeight'length);
Count: 24
Threshold: 1
Signal assignment statement on line 196:
196: sSoftRst <= '0';
Count: 24
Threshold: 1
Signal assignment statement on line 201:
201: sSoftRst <= '0';
Count: 554
Threshold: 1
If statement on lines 203 to 205:
203: if (sBValid = '1' and s_axi_ctrl_bready = '1') then
204: sBValid <= '0';
205: end if;
Count: 554
Threshold: 1
Signal assignment statement on line 204:
204: sBValid <= '0';
Count: 36
Threshold: 1
If statement on lines 207 to 238:
207: if (sWrHandshake = '1') then
208: sBValid <= '1';
...
237: end if;
238: end if;
Count: 554
Threshold: 1
Signal assignment statement on line 208:
208: sBValid <= '1';
Count: 36
Threshold: 1
Variable assignment statement on line 209:
209: vAddrWord := to_integer(unsigned(s_axi_ctrl_awaddr(7 downto 2)));
Count: 36
Threshold: 1
If statement on lines 213 to 237:
213: if (sSoftRst = '0') then
214:
...
236:
237: end if;
Count: 36
Threshold: 1
Sequential statement on lines 215 to 235:
215: case vAddrWord is
216:
...
234:
235: end case;
Count: 36
Threshold: 1
Signal assignment statement on line 219:
219: sWidth <= merge_clamp_dim(sWidth, s_axi_ctrl_wdata, s_axi_ctrl_wstrb, CO_MIN_IMAGE_WIDTH, MAX_IMAGE_WIDTH);
Count: 21
Threshold: 1
Signal assignment statement on line 223:
223: sHeight <= merge_clamp_dim(sHeight, s_axi_ctrl_wdata, s_axi_ctrl_wstrb, CO_MIN_IMAGE_HEIGHT, MAX_IMAGE_HEIGHT);
Count: 6
Threshold: 1
If statement on lines 227 to 229:
227: if (s_axi_ctrl_wstrb(0) = '1' and s_axi_ctrl_wdata(0) = '1') then
228: sSoftRst <= '1';
229: end if;
Count: 6
Threshold: 1
Signal assignment statement on line 228:
228: sSoftRst <= '1';
Count: 6
Threshold: 1
If statement on lines 248 to 249:
248: sRdHandshake <= '1' when s_axi_ctrl_arvalid = '1' and sRValid = '0' else
249: '0';
Count: 201
Threshold: 1
Signal assignment statement on line 248:
248: sRdHandshake <= '1' when s_axi_ctrl_arvalid = '1' and sRValid = '0' else
Count: 48
Threshold: 1
Signal assignment statement on line 249:
249: '0';
Count: 153
Threshold: 1
Signal assignment statement on line 251:
251: s_axi_ctrl_arready <= sRdHandshake;
Count: 102
Threshold: 1
Signal assignment statement on line 252:
252: s_axi_ctrl_rresp <= "00"; -- OKAY; unmapped reads return zero
Count: 3
Threshold: 1
Signal assignment statement on line 253:
253: s_axi_ctrl_rvalid <= sRValid;
Count: 102
Threshold: 1
Signal assignment statement on line 254:
254: s_axi_ctrl_rdata <= sRData;
Count: 43
Threshold: 1
If statement on lines 262 to 316:
262: if rising_edge(aclk) then
263: if (aresetn = '0') then
...
315: end if;
316: end if;
Count: 1156
Threshold: 1
If statement on lines 263 to 315:
263: if (aresetn = '0') then
264: sRValid <= '0';
...
314: end if;
315: end if;
Count: 578
Threshold: 1
Signal assignment statement on line 264:
264: sRValid <= '0';
Count: 24
Threshold: 1
Signal assignment statement on line 265:
265: sRData <= (others => '0');
Count: 24
Threshold: 1
If statement on lines 267 to 314:
267: if (sRValid = '1' and s_axi_ctrl_rready = '1') then
268: sRValid <= '0';
...
313:
314: end if;
Count: 554
Threshold: 1
Signal assignment statement on line 268:
268: sRValid <= '0';
Count: 48
Threshold: 1
Signal assignment statement on line 270:
270: sRValid <= '1';
Count: 48
Threshold: 1
Variable assignment statement on line 271:
271: vAddrWord := to_integer(unsigned(s_axi_ctrl_araddr(7 downto 2)));
Count: 48
Threshold: 1
Signal assignment statement on line 272:
272: sRData <= (others => '0');
Count: 48
Threshold: 1
Sequential statement on lines 274 to 312:
274: case vAddrWord is
275:
...
311:
312: end case;
Count: 48
Threshold: 1
Signal assignment statement on line 278:
278: sRData <= x"4F4A4C53"; -- "OJLS"
Count: 6
Threshold: 1
Signal assignment statement on line 282:
282: sRData <= VERSION;
Count: 3
Threshold: 1
Signal assignment statement on line 286:
286: sRData(7 downto 0) <= std_logic_vector(to_unsigned(BITNESS, 8));
Count: 3
Threshold: 1
Signal assignment statement on line 287:
287: sRData(15 downto 8) <= std_logic_vector(to_unsigned(OUT_WIDTH / 8, 8));
Count: 3
Threshold: 1
Signal assignment statement on line 291:
291: sRData(15 downto 0) <= std_logic_vector(to_unsigned(MAX_IMAGE_WIDTH, 16));
Count: 3
Threshold: 1
Signal assignment statement on line 292:
292: sRData(31 downto 16) <= std_logic_vector(to_unsigned(MAX_IMAGE_HEIGHT, 16));
Count: 3
Threshold: 1
Signal assignment statement on line 296:
296: sRData(15 downto 0) <= std_logic_vector(sWidth);
Count: 18
Threshold: 1
Signal assignment statement on line 300:
300: sRData(15 downto 0) <= std_logic_vector(sHeight);
Count: 6
Threshold: 1
Signal assignment statement on line 304:
304: sRData(0) <= sSoftRst;
Count: 3
Threshold: 1
Signal assignment statement on line 305:
305: sRData(1) <= sReadyMirror;
Count: 3
Threshold: 1
Signal assignment statement on line 324:
324: sCoreRst <= (not aresetn) or sSoftRst;
Count: 21
Threshold: 1
Signal assignment statement on line 326:
326: s_axis_pixel_tready <= sReadyMirror;
Count: 21
Threshold: 1