NVC code coverage report

File	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
openjls_top.vhd	99.3 % (289/291)	97.9 % (94/96)	N.A.	N.A.	N.A.	N.A.	98.9 % (383/387)

Uncovered statements:

Signal assignment statement on line 1034:

1034: sS3CqP1 <= to_signed(MAX_C, C_WIDTH) when sS3CqBase = to_signed(MAX_C, C_WIDTH) else
Count: 0
Threshold: 1

Signal assignment statement on line 1036:

1036: sS3CqM1 <= to_signed(MIN_C, C_WIDTH) when sS3CqBase = to_signed(MIN_C, C_WIDTH) else
Count: 0
Threshold: 1

Excluded statements:

Covered statements:

If statement on lines 473 to 487:

473:    if rising_edge(iClk) then 
474:      if (iRst = '1') then 
...
486:      end if; 
487:    end if;

Count: 204414
Threshold: 1

If statement on lines 474 to 486:

474:      if (iRst = '1') then 
475:        sBsAlmostFullReg <= '0'; 
...
485:        end if; 
486:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 475:

475: sBsAlmostFullReg <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 476:

476: sStallDelay <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 477:

477: sStallLogic <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 479:

479: sBsAlmostFullReg <= sBsAlmostFull;
Count: 101929
Threshold: 1

Signal assignment statement on line 480:

480: sStallDelay <= sStall;
Count: 101929
Threshold: 1

If statement on lines 481 to 485:

481:        if (sStallDelay = '1' and sStall = '1') then 
482:          sStallLogic <= '1'; 
483:        else 
484:          sStallLogic <= '0'; 
485:        end if;

Count: 101929
Threshold: 1

Signal assignment statement on line 482:

482: sStallLogic <= '1';
Count: 3925
Threshold: 1

Signal assignment statement on line 484:

484: sStallLogic <= '0';
Count: 98004
Threshold: 1

Signal assignment statement on line 494:

494: sStall <= sBsAlmostFullReg;
Count: 28
Threshold: 1

Signal assignment statement on line 499:

499: sStallUpstream <= sStall or sStallLogic;
Count: 46
Threshold: 1

If statement on lines 506 to 507:

506:  sCE1 <= '1' when sStallLogic = '0' and (sReg1V = '1' or sValid = '1') else 
507:          '0';

Count: 22656
Threshold: 1

Signal assignment statement on line 506:

506: sCE1 <= '1' when sStallLogic = '0' and (sReg1V = '1' or sValid = '1') else
Count: 20664
Threshold: 1

Signal assignment statement on line 507:

507: '0';
Count: 1992
Threshold: 1

If statement on lines 508 to 509:

508:  sCE2 <= '1' when sStallLogic = '0' and (sReg2V = '1' or sReg1V = '1') else 
509:          '0';

Count: 22644
Threshold: 1

Signal assignment statement on line 508:

508: sCE2 <= '1' when sStallLogic = '0' and (sReg2V = '1' or sReg1V = '1') else
Count: 20656
Threshold: 1

Signal assignment statement on line 509:

509: '0';
Count: 1988
Threshold: 1

If statement on lines 510 to 511:

510:  sCE3 <= '1' when sStallLogic = '0' and (sReg3V = '1' or sReg2V = '1') else 
511:          '0';

Count: 22640
Threshold: 1

Signal assignment statement on line 510:

510: sCE3 <= '1' when sStallLogic = '0' and (sReg3V = '1' or sReg2V = '1') else
Count: 20656
Threshold: 1

Signal assignment statement on line 511:

511: '0';
Count: 1984
Threshold: 1

If statement on lines 512 to 513:

512:  sCE4 <= '1' when sStallLogic = '0' and (sReg4V = '1' or sReg3V = '1') else 
513:          '0';

Count: 22636
Threshold: 1

Signal assignment statement on line 512:

512: sCE4 <= '1' when sStallLogic = '0' and (sReg4V = '1' or sReg3V = '1') else
Count: 20652
Threshold: 1

Signal assignment statement on line 513:

513: '0';
Count: 1984
Threshold: 1

If statement on lines 514 to 515:

514:  sCE5 <= '1' when sStallLogic = '0' and (sReg5V = '1' or sReg4V = '1') else 
515:          '0';

Count: 22624
Threshold: 1

Signal assignment statement on line 514:

514: sCE5 <= '1' when sStallLogic = '0' and (sReg5V = '1' or sReg4V = '1') else
Count: 20644
Threshold: 1

Signal assignment statement on line 515:

515: '0';
Count: 1980
Threshold: 1

If statement on lines 516 to 517:

516:  sCE6 <= '1' when sStallLogic = '0' and (sReg6V = '1' or sReg5V = '1') else 
517:          '0';

Count: 22616
Threshold: 1

Signal assignment statement on line 516:

516: sCE6 <= '1' when sStallLogic = '0' and (sReg6V = '1' or sReg5V = '1') else
Count: 20636
Threshold: 1

Signal assignment statement on line 517:

517: '0';
Count: 1980
Threshold: 1

Signal assignment statement on line 519:

519: sReadyOut <= not iRst and not sStallUpstream; -- Stalls upstream
Count: 164
Threshold: 1

Signal assignment statement on line 520:

520: oReady <= sReadyOut;
Count: 154
Threshold: 1

If statement on lines 538 to 588:

538:    if rising_edge(iClk) then 
539:      if (iRst = '1') then 
...
587:      end if; 
588:    end if;

Count: 204414
Threshold: 1

If statement on lines 539 to 587:

539:      if (iRst = '1') then 
540:        sValid <= '0'; 
...
586:        end if; 
587:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 540:

540: sValid <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 541:

541: sPixel <= (others => '0');
Count: 278
Threshold: 1

Variable assignment statement on line 543:

543: vImageWidthUnsi := unsigned(iImageWidth);
Count: 278
Threshold: 1

Variable assignment statement on line 544:

544: vImageHeightUnsi := unsigned(iImageHeight);
Count: 278
Threshold: 1

If statement on lines 548 to 562:

548:        if (vImageWidthUnsi < CO_MIN_IMAGE_WIDTH) then 
549:          assert false 
...
561:          sImageWidth <= resize(vImageWidthUnsi, sImageWidth'length); 
562:        end if;

Count: 278
Threshold: 1

Assertion statement on lines 549 to 551:

549:          assert false 
550:            report "iImageWidth smaller than the minimum allowed: " & integer'image(CO_MIN_IMAGE_WIDTH) & ", using max value instead: " & integer'image(MAX_IMAGE_WIDTH) 
551:            severity warning;

Count: 16
Threshold: 1

Signal assignment statement on line 553:

553: sImageWidth <= to_unsigned(MAX_IMAGE_WIDTH, sImageWidth'length);
Count: 16
Threshold: 1

Assertion statement on lines 555 to 557:

555:          assert false 
556:            report "iImageWidth larger than the maximum allowed: " & integer'image(MAX_IMAGE_WIDTH) & ", using max value instead: " & integer'image(MAX_IMAGE_WIDTH) 
557:            severity warning;

Count: 16
Threshold: 1

Signal assignment statement on line 559:

559: sImageWidth <= to_unsigned(MAX_IMAGE_WIDTH, sImageWidth'length);
Count: 16
Threshold: 1

Signal assignment statement on line 561:

561: sImageWidth <= resize(vImageWidthUnsi, sImageWidth'length);
Count: 246
Threshold: 1

If statement on lines 564 to 578:

564:        if (vImageHeightUnsi < CO_MIN_IMAGE_HEIGHT) then 
565:          assert false 
...
577:          sImageHeight <= resize(vImageHeightUnsi, sImageHeight'length); 
578:        end if;

Count: 278
Threshold: 1

Assertion statement on lines 565 to 567:

565:          assert false 
566:            report "iImageHeight smaller than the minimum allowed: " & integer'image(CO_MIN_IMAGE_HEIGHT) & ", using max value instead: " & integer'image(MAX_IMAGE_HEIGHT) 
567:            severity warning;

Count: 16
Threshold: 1

Signal assignment statement on line 569:

569: sImageHeight <= to_unsigned(MAX_IMAGE_HEIGHT, sImageHeight'length);
Count: 16
Threshold: 1

Assertion statement on lines 571 to 573:

571:          assert false 
572:            report "iImageHeight larger than the maximum allowed: " & integer'image(MAX_IMAGE_HEIGHT) & ", using max value instead: " & integer'image(MAX_IMAGE_HEIGHT) 
573:            severity warning;

Count: 16
Threshold: 1

Signal assignment statement on line 575:

575: sImageHeight <= to_unsigned(MAX_IMAGE_HEIGHT, sImageHeight'length);
Count: 16
Threshold: 1

Signal assignment statement on line 577:

577: sImageHeight <= resize(vImageHeightUnsi, sImageHeight'length);
Count: 246
Threshold: 1

If statement on lines 580 to 586:

580:        if (iValid = '1' and sReadyOut = '1' and sStallLogic = '0') then -- handshake 
581:          sPixel <= unsigned(iPixel); 
...
585:          sValid <= '0'; 
586:        end if;

Count: 101929
Threshold: 1

Signal assignment statement on line 581:

581: sPixel <= unsigned(iPixel);
Count: 85348
Threshold: 1

Signal assignment statement on line 582:

582: sValid <= '1';
Count: 85348
Threshold: 1

Signal assignment statement on line 584:

584: sPixel <= (others => '0');
Count: 16581
Threshold: 1

Signal assignment statement on line 585:

585: sValid <= '0';
Count: 16581
Threshold: 1

If statement on lines 651 to 692:

651:    if rising_edge(iClk) then 
652:      if (iRst = '1') then 
...
691:      end if; 
692:    end if;

Count: 204414
Threshold: 1

If statement on lines 652 to 691:

652:      if (iRst = '1') then 
653:        sReg1    <= CO_TOKEN_NONE; 
...
690:        sReg1D3 <= sS1D3; 
691:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 653:

653: sReg1 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 654:

654: sReg1V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 655:

655: sReg1Eol <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 656:

656: sReg1Eoi <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 657:

657: sReg1D1 <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 658:

658: sReg1D2 <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 659:

659: sReg1D3 <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 660:

660: sGenPar <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 661:

661: sReg1Par <= '0';
Count: 278
Threshold: 1

If statement on lines 663 to 669:

663:        if (sLbValid = '1' and (sS1ModeRun = '1' or sS1InRunNext = '1')) then 
664:          v.mode := token_run; 
...
668:          v := CO_TOKEN_NONE; 
669:        end if;

Count: 92800
Threshold: 1

Variable assignment statement on line 664:

664: v.mode := token_run;
Count: 992
Threshold: 1

Variable assignment statement on line 666:

666: v.mode := token_regular;
Count: 84320
Threshold: 1

Variable assignment statement on line 668:

668: v := CO_TOKEN_NONE;
Count: 7488
Threshold: 1

If statement on lines 671 to 676:

671:        if (sLbValid = '1') then 
672:          v.Ix := sPixel; 
673:          v.Ra := sLbRa; 
674:          v.Rb := sLbRb; 
675:          v.Rc := sLbRc; 
676:        end if;

Count: 92800
Threshold: 1

Variable assignment statement on line 672:

672: v.Ix := sPixel;
Count: 85312
Threshold: 1

Variable assignment statement on line 673:

673: v.Ra := sLbRa;
Count: 85312
Threshold: 1

Variable assignment statement on line 674:

674: v.Rb := sLbRb;
Count: 85312
Threshold: 1

Variable assignment statement on line 675:

675: v.Rc := sLbRc;
Count: 85312
Threshold: 1

Signal assignment statement on line 678:

678: sReg1 <= v;
Count: 92800
Threshold: 1

Signal assignment statement on line 679:

679: sReg1V <= sValid;
Count: 92800
Threshold: 1

Signal assignment statement on line 680:

680: sReg1Eol <= sLbValid and sLbEol;
Count: 92800
Threshold: 1

Signal assignment statement on line 681:

681: sReg1Eoi <= sLbValid and sLbEoi;
Count: 92800
Threshold: 1

Signal assignment statement on line 684:

684: sReg1Par <= sGenPar;
Count: 92800
Threshold: 1

If statement on lines 685 to 687:

685:        if (sLbValid = '1' and sLbEoi = '1') then 
686:          sGenPar <= not sGenPar; 
687:        end if;

Count: 92800
Threshold: 1

Signal assignment statement on line 686:

686: sGenPar <= not sGenPar;
Count: 165
Threshold: 1

Signal assignment statement on line 688:

688: sReg1D1 <= sS1D1;
Count: 92800
Threshold: 1

Signal assignment statement on line 689:

689: sReg1D2 <= sS1D2;
Count: 92800
Threshold: 1

Signal assignment statement on line 690:

690: sReg1D3 <= sS1D3;
Count: 92800
Threshold: 1

If statement on lines 750 to 751:

750:  sReg1ModeRun <= '1' when sReg1.mode = token_run else 
751:                  '0';

Count: 15772
Threshold: 1

Signal assignment statement on line 750:

750: sReg1ModeRun <= '1' when sReg1.mode = token_run else
Count: 549
Threshold: 1

Signal assignment statement on line 751:

751: '0';
Count: 15223
Threshold: 1

If statement on lines 806 to 816:

806:    if rising_edge(iClk) then 
807:      if (iRst = '1') then 
...
815:      end if; 
816:    end if;

Count: 204414
Threshold: 1

If statement on lines 807 to 815:

807:      if (iRst = '1') then 
808:        sRunCntReg <= (others => '0'); 
...
814:        end if; 
815:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 808:

808: sRunCntReg <= (others => '0');
Count: 278
Threshold: 1

If statement on lines 810 to 814:

810:        if (sS2RunContinue = '1') then 
811:          sRunCntReg <= sS2RunCnt; 
812:        else 
813:          sRunCntReg <= (others => '0'); 
814:        end if;

Count: 988
Threshold: 1

Signal assignment statement on line 811:

811: sRunCntReg <= sS2RunCnt;
Count: 451
Threshold: 1

Signal assignment statement on line 813:

813: sRunCntReg <= (others => '0');
Count: 537
Threshold: 1

If statement on lines 821 to 824:

821:  sS2TokenMode <= token_regular when sReg1.mode = token_regular else 
822:                  token_run_interruption when sS2RiValid = '1' else 
823:                  token_raw when sS2RawValid = '1' else 
824:                  token_none;

Count: 18046
Threshold: 1

Signal assignment statement on line 821:

821: sS2TokenMode <= token_regular when sReg1.mode = token_regular else
Count: 8098
Threshold: 1

Signal assignment statement on line 822:

822: token_run_interruption when sS2RiValid = '1' else
Count: 549
Threshold: 1

Signal assignment statement on line 823:

823: token_raw when sS2RawValid = '1' else
Count: 895
Threshold: 1

Signal assignment statement on line 824:

824: token_none;
Count: 8504
Threshold: 1

If statement on lines 827 to 829:

827:  sS2Q <= sS2QReg when sReg1.mode = token_regular else 
828:          to_unsigned(366, 9) when sS2RItype = '1' else 
829:          to_unsigned(365, 9);

Count: 208810
Threshold: 1

Signal assignment statement on line 827:

827: sS2Q <= sS2QReg when sReg1.mode = token_regular else
Count: 174580
Threshold: 1

Signal assignment statement on line 828:

828: to_unsigned(366, 9) when sS2RItype = '1' else
Count: 26676
Threshold: 1

Signal assignment statement on line 829:

829: to_unsigned(365, 9);
Count: 7554
Threshold: 1

If statement on lines 836 to 842:

836:    if rising_edge(iClk) then 
837:      if (iRst = '1') then 
...
841:      end if; 
842:    end if;

Count: 204414
Threshold: 1

If statement on lines 837 to 841:

837:      if (iRst = '1') then 
838:        sCtxOwnerPar <= '0'; 
839:      elsif (sReg1V = '1') then 
840:        sCtxOwnerPar <= sReg1Par; 
841:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 838:

838: sCtxOwnerPar <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 840:

840: sCtxOwnerPar <= sReg1Par;
Count: 85280
Threshold: 1

If statement on lines 846 to 847:

846:  sCtxRdPar <= sReg1Par when sReg1V = '1' else 
847:               sCtxOwnerPar;

Count: 15250
Threshold: 1

Signal assignment statement on line 846:

846: sCtxRdPar <= sReg1Par when sReg1V = '1' else
Count: 7687
Threshold: 1

Signal assignment statement on line 847:

847: sCtxOwnerPar;
Count: 7563
Threshold: 1

Signal assignment statement on lines 851 to 854:

851:  sCtxWrEn <= sReg3V and 
852:              bool2bit(sReg3Par = sCtxRdPar) and 
853:              (bool2bit(sReg3.mode = token_regular) or 
854:               bool2bit(sReg3.mode = token_run_interruption));

Count: 16153
Threshold: 1

If statement on lines 859 to 867:

859:  sCtxWrData <= std_logic_vector(resize(sS4AqNew, A_STORED)) & 
860:                std_logic_vector(resize(unsigned(-sS4BqNew), B_STORED)) & 
...
866:                std_logic_vector(to_signed(0, C_STORED)) & 
867:                std_logic_vector(sNqEncRi);

Count: 439928
Threshold: 1

Signal assignment statement on lines 859 to 862:

859:  sCtxWrData <= std_logic_vector(resize(sS4AqNew, A_STORED)) & 
860:                std_logic_vector(resize(unsigned(-sS4BqNew), B_STORED)) & 
861:                std_logic_vector(sS4CqNew) & 
862:                std_logic_vector(sNqEncReg)

Count: 399865
Threshold: 1

Signal assignment statement on lines 864 to 867:

864:                std_logic_vector(resize(sS4RiAqNew, A_STORED)) & 
865:                std_logic_vector(sS4RiNnNew) & 
866:                std_logic_vector(to_signed(0, C_STORED)) & 
867:                std_logic_vector(sNqEncRi);

Count: 40063
Threshold: 1

If statement on lines 869 to 870:

869:  sNqEncReg <= (others => '0') when sS4NqNew = to_unsigned(RESET, N_WIDTH) else 
870:               resize(sS4NqNew, N_STORED);

Count: 89521
Threshold: 1

Signal assignment statement on line 869:

869: sNqEncReg <= (others => '0') when sS4NqNew = to_unsigned(RESET, N_WIDTH) else
Count: 1570
Threshold: 1

Signal assignment statement on line 870:

870: resize(sS4NqNew, N_STORED);
Count: 87951
Threshold: 1

If statement on lines 872 to 873:

872:  sNqEncRi <= (others => '0') when sS4RiNqNew = to_unsigned(RESET, N_WIDTH) else 
873:              resize(sS4RiNqNew, N_STORED);

Count: 89501
Threshold: 1

Signal assignment statement on line 872:

872: sNqEncRi <= (others => '0') when sS4RiNqNew = to_unsigned(RESET, N_WIDTH) else
Count: 1570
Threshold: 1

Signal assignment statement on line 873:

873: resize(sS4RiNqNew, N_STORED);
Count: 87931
Threshold: 1

If statement on lines 901 to 903:

901:  sS3Aq <= sS4AqNew when sFwdRegHit = '1' else 
902:           sS4RiAqNew when sFwdRiHit = '1' else 
903:           resize(unsigned(sCtxRdData(CTX_A_HI downto CTX_A_LO)), A_WIDTH);

Count: 278892
Threshold: 1

Signal assignment statement on line 901:

901: sS3Aq <= sS4AqNew when sFwdRegHit = '1' else
Count: 66095
Threshold: 1

Signal assignment statement on line 902:

902: sS4RiAqNew when sFwdRiHit = '1' else
Count: 12
Threshold: 1

Signal assignment statement on line 903:

903: resize(unsigned(sCtxRdData(CTX_A_HI downto CTX_A_LO)), A_WIDTH);
Count: 212785
Threshold: 1

If statement on lines 906 to 907:

906:  sS3Bq <= sS4BqNew when sFwdRegHit = '1' else 
907:           - signed(resize(unsigned(sCtxRdData(CTX_B_HI downto CTX_B_LO)), B_WIDTH));

Count: 252391
Threshold: 1

Signal assignment statement on line 906:

906: sS3Bq <= sS4BqNew when sFwdRegHit = '1' else
Count: 61039
Threshold: 1

Signal assignment statement on line 907:

907: - signed(resize(unsigned(sCtxRdData(CTX_B_HI downto CTX_B_LO)), B_WIDTH));
Count: 191352
Threshold: 1

If statement on lines 910 to 911:

910:  sS3Cq <= sS4CqNew when sFwdRegHit = '1' else 
911:           signed(sCtxRdData(CTX_C_HI downto CTX_C_LO));

Count: 197363
Threshold: 1

Signal assignment statement on line 910:

910: sS3Cq <= sS4CqNew when sFwdRegHit = '1' else
Count: 51057
Threshold: 1

Signal assignment statement on line 911:

911: signed(sCtxRdData(CTX_C_HI downto CTX_C_LO));
Count: 146306
Threshold: 1

If statement on lines 913 to 916:

913:  sS3Nq <= sS4NqNew when sFwdRegHit = '1' else 
914:           sS4RiNqNew when sFwdRiHit = '1' else 
915:           to_unsigned(RESET, N_WIDTH) when unsigned(sCtxRdData(CTX_N_HI downto CTX_N_LO)) = 0 else 
916:           resize(unsigned(sCtxRdData(CTX_N_HI downto CTX_N_LO)), N_WIDTH);

Count: 183545
Threshold: 1

Signal assignment statement on line 913:

913: sS3Nq <= sS4NqNew when sFwdRegHit = '1' else
Count: 43640
Threshold: 1

Signal assignment statement on line 914:

914: sS4RiNqNew when sFwdRiHit = '1' else
Count: 8
Threshold: 1

Signal assignment statement on line 915:

915:           to_unsigned(RESET, N_WIDTH) when unsigned(sCtxRdData(CTX_N_HI downto CTX_N_LO)) = 0 else

Count: 2648
Threshold: 1

Signal assignment statement on line 916:

916: resize(unsigned(sCtxRdData(CTX_N_HI downto CTX_N_LO)), N_WIDTH);
Count: 137249
Threshold: 1

If statement on lines 920 to 922:

920:  sS3Nn <= sS4RiNnNew when sFwdRiHit = '1' else 
921:           (others => '0') when sReg2.mode = token_regular else 
922:           unsigned(sCtxRdData(CTX_NN_HI downto CTX_NN_LO));

Count: 124653
Threshold: 1

Signal assignment statement on line 920:

920: sS3Nn <= sS4RiNnNew when sFwdRiHit = '1' else
Count: 8
Threshold: 1

Signal assignment statement on line 921:

921: (others => '0') when sReg2.mode = token_regular else
Count: 111369
Threshold: 1

Signal assignment statement on line 922:

922: unsigned(sCtxRdData(CTX_NN_HI downto CTX_NN_LO));
Count: 13276
Threshold: 1

If statement on lines 944 to 1000:

944:    if rising_edge(iClk) then 
945:      if (iRst = '1') then 
...
999:      end if; 
1000:    end if;

Count: 204414
Threshold: 1

If statement on lines 945 to 999:

945:      if (iRst = '1') then 
946:        sReg2    <= CO_TOKEN_NONE; 
...
998:        sReg2Par <= sReg1Par; 
999:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 946:

946: sReg2 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 947:

947: sReg2V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 948:

948: sReg2Eoi <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 949:

949: sReg2Px <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 950:

950: sReg2Par <= '0';
Count: 278
Threshold: 1

Variable assignment statement on line 954:

954: v := CO_TOKEN_NONE;
Count: 92768
Threshold: 1

Variable assignment statement on line 955:

955: v.mode := sS2TokenMode;
Count: 92768
Threshold: 1

Variable assignment statement on line 956:

956: v.Q := sS2Q;
Count: 92768
Threshold: 1

Sequential statement on lines 958 to 988:

958:        case sS2TokenMode is 
959: 
...
987: 
988:        end case;

Count: 92768
Threshold: 1

Variable assignment statement on line 962:

962: v.Ix := sReg1.Ix;
Count: 84292
Threshold: 1

Variable assignment statement on line 963:

963: v.Ra := sReg1.Ra;
Count: 84292
Threshold: 1

Variable assignment statement on line 964:

964: v.Rb := sReg1.Rb;
Count: 84292
Threshold: 1

Variable assignment statement on line 965:

965: v.Rc := sReg1.Rc;
Count: 84292
Threshold: 1

Variable assignment statement on line 966:

966: v.Sign := sS2MSign;
Count: 84292
Threshold: 1

Variable assignment statement on line 970:

970: v.Ix := sS2RiIx;
Count: 421
Threshold: 1

Variable assignment statement on line 971:

971: v.Ra := sS2RiRa;
Count: 421
Threshold: 1

Variable assignment statement on line 972:

972: v.Rb := sS2RiRb;
Count: 421
Threshold: 1

Variable assignment statement on line 973:

973: v.RiType := sS2RItype;
Count: 421
Threshold: 1

Variable assignment statement on line 974:

974: v.Errval := resize(sS2RiErr18, v.Errval'length);
Count: 421
Threshold: 1

Variable assignment statement on line 975:

975: v.RawLen := resize(sS2RawLen, v.RawLen'length);
Count: 421
Threshold: 1

Variable assignment statement on line 976:

976: v.RawVal := resize(sS2RawVal, v.RawVal'length);
Count: 421
Threshold: 1

Variable assignment statement on line 977:

977: v.RiRunIndex := sS2RiRunIndex;
Count: 421
Threshold: 1

Variable assignment statement on line 981:

981: v.RawLen := resize(sS2RawLen, v.RawLen'length);
Count: 567
Threshold: 1

Variable assignment statement on line 982:

982: v.RawVal := resize(sS2RawVal, v.RawVal'length);
Count: 567
Threshold: 1

Variable assignment statement on line 986:

986: v := CO_TOKEN_NONE;
Count: 7488
Threshold: 1

If statement on lines 990 to 992:

990:        if (sReg1V = '0' or sS2TokenMode = token_none) then 
991:          v := CO_TOKEN_NONE; 
992:        end if;

Count: 92768
Threshold: 1

Variable assignment statement on line 991:

991: v := CO_TOKEN_NONE;
Count: 7488
Threshold: 1

Signal assignment statement on line 994:

994: sReg2 <= v;
Count: 92768
Threshold: 1

Signal assignment statement on line 995:

995: sReg2V <= sReg1V and bool2bit(sS2TokenMode /= token_none);
Count: 92768
Threshold: 1

Signal assignment statement on line 996:

996: sReg2Eoi <= sReg1Eoi;
Count: 92768
Threshold: 1

Signal assignment statement on line 997:

997: sReg2Px <= sS2Px;
Count: 92768
Threshold: 1

Signal assignment statement on line 998:

998: sReg2Par <= sReg1Par;
Count: 92768
Threshold: 1

Signal assignment statement on line 1008:

1008: sS3Px <= sReg2Px;
Count: 91719
Threshold: 1

If statement on lines 1016 to 1020:

1016:  sFwdRegHit <= '1' when sReg2V = '1' and sReg3V = '1' 
1017:                         and sReg2Par = sReg3Par 
1018:                         and sReg2.Q = sReg3.Q 
1019:                         and sReg3.mode = token_regular else 
1020:                '0';

Count: 80100
Threshold: 1

Signal assignment statement on line 1016:

1016: sFwdRegHit <= '1' when sReg2V = '1' and sReg3V = '1'
Count: 7360
Threshold: 1

Signal assignment statement on line 1020:

1020: '0';
Count: 72740
Threshold: 1

If statement on lines 1022 to 1026:

1022:  sFwdRiHit <= '1' when sReg2V = '1' and sReg3V = '1' 
1023:                        and sReg2Par = sReg3Par 
1024:                        and sReg2.Q = sReg3.Q 
1025:                        and sReg3.mode = token_run_interruption else 
1026:               '0';

Count: 80100
Threshold: 1

Signal assignment statement on line 1022:

1022: sFwdRiHit <= '1' when sReg2V = '1' and sReg3V = '1'
Count: 4
Threshold: 1

Signal assignment statement on line 1026:

1026: '0';
Count: 80096
Threshold: 1

If statement on lines 1030 to 1031:

1030:  sS3CqBase <= sReg3.Cq when sFwdRegHit = '1' else 
1031:               sS3Cq;

Count: 203420
Threshold: 1

Signal assignment statement on line 1030:

1030: sS3CqBase <= sReg3.Cq when sFwdRegHit = '1' else
Count: 62676
Threshold: 1

Signal assignment statement on line 1031:

1031: sS3Cq;
Count: 140744
Threshold: 1

If statement on lines 1034 to 1035:

1034:  sS3CqP1 <= to_signed(MAX_C, C_WIDTH) when sS3CqBase = to_signed(MAX_C, C_WIDTH) else 
1035:             sS3CqBase + 1;

Count: 87373
Threshold: 1

Signal assignment statement on line 1035:

1035: sS3CqBase + 1;
Count: 87373
Threshold: 1

If statement on lines 1036 to 1037:

1036:  sS3CqM1 <= to_signed(MIN_C, C_WIDTH) when sS3CqBase = to_signed(MIN_C, C_WIDTH) else 
1037:             sS3CqBase - 1;

Count: 87373
Threshold: 1

Signal assignment statement on line 1037:

1037: sS3CqBase - 1;
Count: 87373
Threshold: 1

Signal assignment statement on line 1136:

1136: sDeltaCq <= sS4CqNew - sReg3.Cq;
Count: 229979
Threshold: 1

If statement on lines 1138 to 1139:

1138:  sSpecUseM <= '1' when sFwdRegHit = '1' and sDeltaCq < 0 else 
1139:               '0';

Count: 231078
Threshold: 1

Signal assignment statement on line 1138:

1138: sSpecUseM <= '1' when sFwdRegHit = '1' and sDeltaCq < 0 else
Count: 18284
Threshold: 1

Signal assignment statement on line 1139:

1139: '0';
Count: 212794
Threshold: 1

If statement on lines 1140 to 1141:

1140:  sSpecUseP <= '1' when sFwdRegHit = '1' and sDeltaCq > 0 else 
1141:               '0';

Count: 231078
Threshold: 1

Signal assignment statement on line 1140:

1140: sSpecUseP <= '1' when sFwdRegHit = '1' and sDeltaCq > 0 else
Count: 17013
Threshold: 1

Signal assignment statement on line 1141:

1141: '0';
Count: 214065
Threshold: 1

If statement on lines 1143 to 1145:

1143:  sS3Err9Sel <= sS3Err9M when sSpecUseM = '1' else 
1144:                sS3Err9P when sSpecUseP = '1' else 
1145:                sS3Err9C;

Count: 431142
Threshold: 1

Signal assignment statement on line 1143:

1143: sS3Err9Sel <= sS3Err9M when sSpecUseM = '1' else
Count: 36832
Threshold: 1

Signal assignment statement on line 1144:

1144: sS3Err9P when sSpecUseP = '1' else
Count: 33872
Threshold: 1

Signal assignment statement on line 1145:

1145: sS3Err9C;
Count: 360438
Threshold: 1

If statement on lines 1186 to 1227:

1186:    if rising_edge(iClk) then 
1187:      if (iRst = '1') then 
...
1226:      end if; 
1227:    end if;

Count: 204414
Threshold: 1

If statement on lines 1187 to 1226:

1187:      if (iRst = '1') then 
1188:        sReg3    <= CO_TOKEN_NONE; 
...
1225:        sReg3Par <= sReg2Par; 
1226:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1188:

1188: sReg3 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 1189:

1189: sReg3V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1190:

1190: sReg3Eoi <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1191:

1191: sReg3Par <= '0';
Count: 278
Threshold: 1

Variable assignment statement on line 1193:

1193: v := sReg2;
Count: 92740
Threshold: 1

Variable assignment statement on line 1194:

1194: v.Aq := sS3Aq;
Count: 92740
Threshold: 1

Variable assignment statement on line 1195:

1195: v.Bq := sS3Bq;
Count: 92740
Threshold: 1

Variable assignment statement on line 1196:

1196: v.Cq := sS3Cq;
Count: 92740
Threshold: 1

Variable assignment statement on line 1197:

1197: v.Nq := sS3Nq;
Count: 92740
Threshold: 1

Variable assignment statement on line 1198:

1198: v.Nn := sS3Nn;
Count: 92740
Threshold: 1

Variable assignment statement on line 1199:

1199: v.Temp := (others => '0');
Count: 92740
Threshold: 1

Sequential statement on lines 1201 to 1217:

1201:        case sReg2.mode is 
1202: 
...
1216: 
1217:        end case;

Count: 92740
Threshold: 1

Variable assignment statement on line 1205:

1205: v.Errval := resize(sS3Err9Sel, v.Errval'length);
Count: 84268
Threshold: 1

Variable assignment statement on line 1209:

1209: v.Errval := resize(sS3RiErr19, v.Errval'length);
Count: 417
Threshold: 1

Variable assignment statement on line 1210:

1210: v.Sign := sS3RiSign;
Count: 417
Threshold: 1

Variable assignment statement on line 1211:

1211: v.Temp := sS3RiTemp;
Count: 417
Threshold: 1

If statement on lines 1219 to 1221:

1219:        if (sReg2V = '0') then 
1220:          v := CO_TOKEN_NONE; 
1221:        end if;

Count: 92740
Threshold: 1

Variable assignment statement on line 1220:

1220: v := CO_TOKEN_NONE;
Count: 7488
Threshold: 1

Signal assignment statement on line 1222:

1222: sReg3 <= v;
Count: 92740
Threshold: 1

Signal assignment statement on line 1223:

1223: sReg3V <= sReg2V;
Count: 92740
Threshold: 1

Signal assignment statement on line 1224:

1224: sReg3Eoi <= sReg2Eoi;
Count: 92740
Threshold: 1

Signal assignment statement on line 1225:

1225: sReg3Par <= sReg2Par;
Count: 92740
Threshold: 1

If statement on lines 1235 to 1236:

1235:  sS4AqSel <= sReg3.Temp when sReg3.mode = token_run_interruption else 
1236:              sReg3.Aq;

Count: 91108
Threshold: 1

Signal assignment statement on line 1235:

1235: sS4AqSel <= sReg3.Temp when sReg3.mode = token_run_interruption else
Count: 417
Threshold: 1

Signal assignment statement on line 1236:

1236: sReg3.Aq;
Count: 90691
Threshold: 1

If statement on lines 1312 to 1327:

1312:    if rising_edge(iClk) then 
1313:      if (iRst = '1') then 
...
1326:      end if; 
1327:    end if;

Count: 204414
Threshold: 1

If statement on lines 1313 to 1326:

1313:      if (iRst = '1') then 
1314:        sReg4    <= CO_TOKEN_NONE; 
...
1325:        sReg4Eoi <= sReg3Eoi; 
1326:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1314:

1314: sReg4 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 1315:

1315: sReg4V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1316:

1316: sReg4Eoi <= '0';
Count: 278
Threshold: 1

Variable assignment statement on line 1318:

1318: v := sReg3;
Count: 92708
Threshold: 1

Variable assignment statement on line 1319:

1319: v.k := resize(sS4K, K_WIDTH);
Count: 92708
Threshold: 1

If statement on lines 1320 to 1322:

1320:        if (sReg3V = '0') then 
1321:          v := CO_TOKEN_NONE; 
1322:        end if;

Count: 92708
Threshold: 1

Variable assignment statement on line 1321:

1321: v := CO_TOKEN_NONE;
Count: 7484
Threshold: 1

Signal assignment statement on line 1323:

1323: sReg4 <= v;
Count: 92708
Threshold: 1

Signal assignment statement on line 1324:

1324: sReg4V <= sReg3V;
Count: 92708
Threshold: 1

Signal assignment statement on line 1325:

1325: sReg4Eoi <= sReg3Eoi;
Count: 92708
Threshold: 1

If statement on lines 1376 to 1377:

1376:  sS5GolMErr <= sS5MErrval when sReg4.mode = token_regular else 
1377:                sS5RiEmErrval;

Count: 249301
Threshold: 1

Signal assignment statement on line 1376:

1376: sS5GolMErr <= sS5MErrval when sReg4.mode = token_regular else
Count: 219433
Threshold: 1

Signal assignment statement on line 1377:

1377: sS5RiEmErrval;
Count: 29868
Threshold: 1

If statement on lines 1388 to 1404:

1388:    if rising_edge(iClk) then 
1389:      if (iRst = '1') then 
...
1403:      end if; 
1404:    end if;

Count: 204414
Threshold: 1

If statement on lines 1389 to 1403:

1389:      if (iRst = '1') then 
1390:        sReg5        <= CO_TOKEN_NONE; 
...
1402:        sReg5GolMErr <= sS5GolMErr; 
1403:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1390:

1390: sReg5 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 1391:

1391: sReg5V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1392:

1392: sReg5Eoi <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1393:

1393: sReg5GolMErr <= (others => '0');
Count: 278
Threshold: 1

Variable assignment statement on line 1395:

1395: v := sReg4;
Count: 92676
Threshold: 1

If statement on lines 1396 to 1398:

1396:        if (sReg4V = '0') then 
1397:          v := CO_TOKEN_NONE; 
1398:        end if;

Count: 92676
Threshold: 1

Variable assignment statement on line 1397:

1397: v := CO_TOKEN_NONE;
Count: 7480
Threshold: 1

Signal assignment statement on line 1399:

1399: sReg5 <= v;
Count: 92676
Threshold: 1

Signal assignment statement on line 1400:

1400: sReg5V <= sReg4V;
Count: 92676
Threshold: 1

Signal assignment statement on line 1401:

1401: sReg5Eoi <= sReg4Eoi;
Count: 92676
Threshold: 1

Signal assignment statement on line 1402:

1402: sReg5GolMErr <= sS5GolMErr;
Count: 92676
Threshold: 1

If statement on lines 1437 to 1457:

1437:    if rising_edge(iClk) then 
1438:      if (iRst = '1') then 
...
1456:      end if; 
1457:    end if;

Count: 204414
Threshold: 1

If statement on lines 1438 to 1456:

1438:      if (iRst = '1') then 
1439:        sReg6       <= CO_TOKEN_NONE; 
...
1455:        sReg6SufVal <= sS5SufVal; 
1456:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1439:

1439: sReg6 <= CO_TOKEN_NONE;
Count: 278
Threshold: 1

Signal assignment statement on line 1440:

1440: sReg6V <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1441:

1441: sReg6Eoi <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1442:

1442: sReg6Unary <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 1443:

1443: sReg6SufLen <= (others => '0');
Count: 278
Threshold: 1

Signal assignment statement on line 1444:

1444: sReg6SufVal <= (others => '0');
Count: 278
Threshold: 1

Variable assignment statement on line 1446:

1446: v := sReg5;
Count: 92640
Threshold: 1

If statement on lines 1447 to 1449:

1447:        if (sReg5V = '0') then 
1448:          v := CO_TOKEN_NONE; 
1449:        end if;

Count: 92640
Threshold: 1

Variable assignment statement on line 1448:

1448: v := CO_TOKEN_NONE;
Count: 7476
Threshold: 1

Signal assignment statement on line 1450:

1450: sReg6 <= v;
Count: 92640
Threshold: 1

Signal assignment statement on line 1451:

1451: sReg6V <= sReg5V;
Count: 92640
Threshold: 1

Signal assignment statement on line 1452:

1452: sReg6Eoi <= sReg5Eoi;
Count: 92640
Threshold: 1

Signal assignment statement on line 1453:

1453: sReg6Unary <= sS5Unary;
Count: 92640
Threshold: 1

Signal assignment statement on line 1454:

1454: sReg6SufLen <= sS5SufLen;
Count: 92640
Threshold: 1

Signal assignment statement on line 1455:

1455: sReg6SufVal <= sS5SufVal;
Count: 92640
Threshold: 1

If statement on lines 1465 to 1467:

1465:  sBpRawV <= '1' when sReg6V = '1' and sStallLogic = '0' 
1466:                      and (sReg6.mode = token_run_interruption or sReg6.mode = token_raw) else 
1467:             '0';

Count: 15890
Threshold: 1

Signal assignment statement on line 1465:

1465: sBpRawV <= '1' when sReg6V = '1' and sStallLogic = '0'
Count: 685
Threshold: 1

Signal assignment statement on line 1467:

1467: '0';
Count: 15205
Threshold: 1

If statement on lines 1468 to 1470:

1468:  sBpGolV <= '1' when sReg6V = '1' and sStallLogic = '0' 
1469:                      and (sReg6.mode = token_regular or sReg6.mode = token_run_interruption) else 
1470:             '0';

Count: 15890
Threshold: 1

Signal assignment statement on line 1468:

1468: sBpGolV <= '1' when sReg6V = '1' and sStallLogic = '0'
Count: 8074
Threshold: 1

Signal assignment statement on line 1470:

1470: '0';
Count: 7816
Threshold: 1

If statement on lines 1559 to 1565:

1559:    if rising_edge(iClk) then 
1560:      if (iRst = '1') then 
...
1564:      end if; 
1565:    end if;

Count: 204414
Threshold: 1

If statement on lines 1560 to 1564:

1560:      if (iRst = '1') then 
1561:        sBsFlush <= '0'; 
1562:      elsif (sStallLogic = '0') then 
1563:        sBsFlush <= sReg6Eoi; 
1564:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1561:

1561: sBsFlush <= '0';
Count: 278
Threshold: 1

Signal assignment statement on line 1563:

1563: sBsFlush <= sReg6Eoi;
Count: 98004
Threshold: 1

Signal assignment statement on line 1569:

1569: sFramerEoi <= sBsFlushDone;
Count: 350
Threshold: 1

If statement on lines 1576 to 1582:

1576:    if rising_edge(iClk) then 
1577:      if (iRst = '1') then 
...
1581:      end if; 
1582:    end if;

Count: 204414
Threshold: 1

If statement on lines 1577 to 1581:

1577:      if (iRst = '1') then 
1578:        sFirstPixel <= '1'; 
1579:      elsif (sValid = '1') then 
1580:        sFirstPixel <= sLbEoi; 
1581:      end if;

Count: 102207
Threshold: 1

Signal assignment statement on line 1578:

1578: sFirstPixel <= '1';
Count: 278
Threshold: 1

Signal assignment statement on line 1580:

1580: sFirstPixel <= sLbEoi;
Count: 85312
Threshold: 1

Signal assignment statement on line 1586:

1586: sFramerStart <= sValid and sFirstPixel;
Count: 15295
Threshold: 1

If statement on lines 1547 to 1548:

1547:    oKeep(OUT_WIDTH / 8 - 1 - i) <= '1' when sFramerVBytes > i else 
1548:                                    '0';

Count: 7462
Threshold: 1

Signal assignment statement on line 1547:

1547: oKeep(OUT_WIDTH / 8 - 1 - i) <= '1' when sFramerVBytes > i else
Count: 3394
Threshold: 1

Signal assignment statement on line 1548:

1548: '0';
Count: 4068
Threshold: 1

Uncovered branches:

"if" / "when" / "else" condition on line 1034:

1034: sS3CqP1 <= to_signed(MAX_C, C_WIDTH) when sS3CqBase = to_signed(MAX_C, C_WIDTH) else

	Evaluated to	Count	Threshold	Exclude Command
Bin	True	0	1

"if" / "when" / "else" condition on line 1036:

1036: sS3CqM1 <= to_signed(MIN_C, C_WIDTH) when sS3CqBase = to_signed(MIN_C, C_WIDTH) else

	Evaluated to	Count	Threshold	Exclude Command
Bin	True	0	1

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 473:

473: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 474:

474: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 481:

481: if (sStallDelay = '1' and sStall = '1') then

	Evaluated to	Count	Threshold
Bin	True	3925	1

"if" / "when" / "else" condition on line 506:

506: sCE1 <= '1' when sStallLogic = '0' and (sReg1V = '1' or sValid = '1') else

	Evaluated to	Count	Threshold
Bin	True	20664	1

"if" / "when" / "else" condition on line 508:

508: sCE2 <= '1' when sStallLogic = '0' and (sReg2V = '1' or sReg1V = '1') else

	Evaluated to	Count	Threshold
Bin	True	20656	1

"if" / "when" / "else" condition on line 510:

510: sCE3 <= '1' when sStallLogic = '0' and (sReg3V = '1' or sReg2V = '1') else

	Evaluated to	Count	Threshold
Bin	True	20656	1

"if" / "when" / "else" condition on line 512:

512: sCE4 <= '1' when sStallLogic = '0' and (sReg4V = '1' or sReg3V = '1') else

	Evaluated to	Count	Threshold
Bin	True	20652	1

"if" / "when" / "else" condition on line 514:

514: sCE5 <= '1' when sStallLogic = '0' and (sReg5V = '1' or sReg4V = '1') else

	Evaluated to	Count	Threshold
Bin	True	20644	1

"if" / "when" / "else" condition on line 516:

516: sCE6 <= '1' when sStallLogic = '0' and (sReg6V = '1' or sReg5V = '1') else

	Evaluated to	Count	Threshold
Bin	True	20636	1

"if" / "when" / "else" condition on line 538:

538: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 539:

539: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 548:

548: if (vImageWidthUnsi < CO_MIN_IMAGE_WIDTH) then

	Evaluated to	Count	Threshold
Bin	True	16	1

"if" / "when" / "else" condition on line 554:

554: elsif (vImageWidthUnsi > MAX_IMAGE_WIDTH) then

	Evaluated to	Count	Threshold
Bin	True	16	1

"if" / "when" / "else" condition on line 564:

564: if (vImageHeightUnsi < CO_MIN_IMAGE_HEIGHT) then

	Evaluated to	Count	Threshold
Bin	True	16	1

"if" / "when" / "else" condition on line 570:

570: elsif (vImageHeightUnsi > MAX_IMAGE_HEIGHT) then

	Evaluated to	Count	Threshold
Bin	True	16	1

"if" / "when" / "else" condition on line 580:

580: if (iValid = '1' and sReadyOut = '1' and sStallLogic = '0') then -- handshake

	Evaluated to	Count	Threshold
Bin	True	85348	1

"if" / "when" / "else" condition on line 651:

651: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 652:

652: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 662:

662: elsif (sCE1 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92800	1

"if" / "when" / "else" condition on line 663:

663: if (sLbValid = '1' and (sS1ModeRun = '1' or sS1InRunNext = '1')) then

	Evaluated to	Count	Threshold
Bin	True	992	1

"if" / "when" / "else" condition on line 665:

665: elsif (sLbValid = '1') then

	Evaluated to	Count	Threshold
Bin	True	84320	1

"if" / "when" / "else" condition on line 671:

671: if (sLbValid = '1') then

	Evaluated to	Count	Threshold
Bin	True	85312	1

"if" / "when" / "else" condition on line 685:

685: if (sLbValid = '1' and sLbEoi = '1') then

	Evaluated to	Count	Threshold
Bin	True	165	1

"if" / "when" / "else" condition on line 750:

750: sReg1ModeRun <= '1' when sReg1.mode = token_run else

	Evaluated to	Count	Threshold
Bin	True	549	1

"if" / "when" / "else" condition on line 806:

806: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 807:

807: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 809:

809: elsif (sStallLogic = '0' and sReg1.mode = token_run) then

	Evaluated to	Count	Threshold
Bin	True	988	1

"if" / "when" / "else" condition on line 810:

810: if (sS2RunContinue = '1') then

	Evaluated to	Count	Threshold
Bin	True	451	1

"if" / "when" / "else" condition on line 821:

821: sS2TokenMode <= token_regular when sReg1.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	8098	1

"if" / "when" / "else" condition on line 822:

822: token_run_interruption when sS2RiValid = '1' else

	Evaluated to	Count	Threshold
Bin	True	549	1

"if" / "when" / "else" condition on line 823:

823: token_raw when sS2RawValid = '1' else

	Evaluated to	Count	Threshold
Bin	True	895	1

"if" / "when" / "else" condition on line 827:

827: sS2Q <= sS2QReg when sReg1.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	174580	1

"if" / "when" / "else" condition on line 828:

828: to_unsigned(366, 9) when sS2RItype = '1' else

	Evaluated to	Count	Threshold
Bin	True	26676	1

"if" / "when" / "else" condition on line 836:

836: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 837:

837: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 839:

839: elsif (sReg1V = '1') then

	Evaluated to	Count	Threshold
Bin	True	85280	1

"if" / "when" / "else" condition on line 846:

846: sCtxRdPar <= sReg1Par when sReg1V = '1' else

	Evaluated to	Count	Threshold
Bin	True	7687	1

"if" / "when" / "else" condition on line 863:

863: when sReg3.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	399865	1

"if" / "when" / "else" condition on line 869:

869: sNqEncReg <= (others => '0') when sS4NqNew = to_unsigned(RESET, N_WIDTH) else

	Evaluated to	Count	Threshold
Bin	True	1570	1

"if" / "when" / "else" condition on line 872:

872: sNqEncRi <= (others => '0') when sS4RiNqNew = to_unsigned(RESET, N_WIDTH) else

	Evaluated to	Count	Threshold
Bin	True	1570	1

"if" / "when" / "else" condition on line 901:

901: sS3Aq <= sS4AqNew when sFwdRegHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	66095	1

"if" / "when" / "else" condition on line 902:

902: sS4RiAqNew when sFwdRiHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	12	1

"if" / "when" / "else" condition on line 906:

906: sS3Bq <= sS4BqNew when sFwdRegHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	61039	1

"if" / "when" / "else" condition on line 910:

910: sS3Cq <= sS4CqNew when sFwdRegHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	51057	1

"if" / "when" / "else" condition on line 913:

913: sS3Nq <= sS4NqNew when sFwdRegHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	43640	1

"if" / "when" / "else" condition on line 914:

914: sS4RiNqNew when sFwdRiHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	8	1

"if" / "when" / "else" condition on line 915:

915:           to_unsigned(RESET, N_WIDTH) when unsigned(sCtxRdData(CTX_N_HI downto CTX_N_LO)) = 0 else

	Evaluated to	Count	Threshold
Bin	True	2648	1

"if" / "when" / "else" condition on line 920:

920: sS3Nn <= sS4RiNnNew when sFwdRiHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	8	1

"if" / "when" / "else" condition on line 921:

921: (others => '0') when sReg2.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	111369	1

"if" / "when" / "else" condition on line 944:

944: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 945:

945: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 951:

951: elsif (sCE2 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92768	1

"case" / "with" / "select" choice on line 960:

960: when token_regular =>

	Choice of	Count	Threshold
Bin	`token_regular`	84292	1

"case" / "with" / "select" choice on line 968:

968: when token_run_interruption =>

	Choice of	Count	Threshold
Bin	`token_run_interruption`	421	1

"case" / "with" / "select" choice on line 979:

979: when token_raw =>

	Choice of	Count	Threshold
Bin	`token_raw`	567	1

"case" / "with" / "select" choice on line 984:

984: when others =>

	Choice of	Count	Threshold
Bin	`others`	7488	1

"if" / "when" / "else" condition on line 990:

990: if (sReg1V = '0' or sS2TokenMode = token_none) then

	Evaluated to	Count	Threshold
Bin	True	7488	1

"if" / "when" / "else" condition on lines 1016 to 1019:

1016:  sFwdRegHit <= '1' when sReg2V = '1' and sReg3V = '1' 
1017:                         and sReg2Par = sReg3Par 
1018:                         and sReg2.Q = sReg3.Q 
1019:                         and sReg3.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	7360	1

"if" / "when" / "else" condition on lines 1022 to 1025:

1022:  sFwdRiHit <= '1' when sReg2V = '1' and sReg3V = '1' 
1023:                        and sReg2Par = sReg3Par 
1024:                        and sReg2.Q = sReg3.Q 
1025:                        and sReg3.mode = token_run_interruption else

	Evaluated to	Count	Threshold
Bin	True	4	1

"if" / "when" / "else" condition on line 1030:

1030: sS3CqBase <= sReg3.Cq when sFwdRegHit = '1' else

	Evaluated to	Count	Threshold
Bin	True	62676	1

"if" / "when" / "else" condition on line 1138:

1138: sSpecUseM <= '1' when sFwdRegHit = '1' and sDeltaCq < 0 else

	Evaluated to	Count	Threshold
Bin	True	18284	1

"if" / "when" / "else" condition on line 1140:

1140: sSpecUseP <= '1' when sFwdRegHit = '1' and sDeltaCq > 0 else

	Evaluated to	Count	Threshold
Bin	True	17013	1

"if" / "when" / "else" condition on line 1143:

1143: sS3Err9Sel <= sS3Err9M when sSpecUseM = '1' else

	Evaluated to	Count	Threshold
Bin	True	36832	1

"if" / "when" / "else" condition on line 1144:

1144: sS3Err9P when sSpecUseP = '1' else

	Evaluated to	Count	Threshold
Bin	True	33872	1

"if" / "when" / "else" condition on line 1186:

1186: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1187:

1187: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1192:

1192: elsif (sCE3 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92740	1

"case" / "with" / "select" choice on line 1203:

1203: when token_regular =>

	Choice of	Count	Threshold
Bin	`token_regular`	84268	1

"case" / "with" / "select" choice on line 1207:

1207: when token_run_interruption =>

	Choice of	Count	Threshold
Bin	`token_run_interruption`	417	1

"case" / "with" / "select" choice on line 1213:

1213: when others =>

	Choice of	Count	Threshold
Bin	`others`	8055	1

"if" / "when" / "else" condition on line 1219:

1219: if (sReg2V = '0') then

	Evaluated to	Count	Threshold
Bin	True	7488	1

"if" / "when" / "else" condition on line 1235:

1235: sS4AqSel <= sReg3.Temp when sReg3.mode = token_run_interruption else

	Evaluated to	Count	Threshold
Bin	True	417	1

"if" / "when" / "else" condition on line 1312:

1312: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1313:

1313: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1317:

1317: elsif (sCE4 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92708	1

"if" / "when" / "else" condition on line 1320:

1320: if (sReg3V = '0') then

	Evaluated to	Count	Threshold
Bin	True	7484	1

"if" / "when" / "else" condition on line 1376:

1376: sS5GolMErr <= sS5MErrval when sReg4.mode = token_regular else

	Evaluated to	Count	Threshold
Bin	True	219433	1

"if" / "when" / "else" condition on line 1388:

1388: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1389:

1389: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1394:

1394: elsif (sCE5 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92676	1

"if" / "when" / "else" condition on line 1396:

1396: if (sReg4V = '0') then

	Evaluated to	Count	Threshold
Bin	True	7480	1

"if" / "when" / "else" condition on line 1437:

1437: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1438:

1438: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1445:

1445: elsif (sCE6 = '1') then

	Evaluated to	Count	Threshold
Bin	True	92640	1

"if" / "when" / "else" condition on line 1447:

1447: if (sReg5V = '0') then

	Evaluated to	Count	Threshold
Bin	True	7476	1

"if" / "when" / "else" condition on lines 1465 to 1466:

1465:  sBpRawV <= '1' when sReg6V = '1' and sStallLogic = '0' 
1466:                      and (sReg6.mode = token_run_interruption or sReg6.mode = token_raw) else

	Evaluated to	Count	Threshold
Bin	True	685	1

"if" / "when" / "else" condition on lines 1468 to 1469:

1468:  sBpGolV <= '1' when sReg6V = '1' and sStallLogic = '0' 
1469:                      and (sReg6.mode = token_regular or sReg6.mode = token_run_interruption) else

	Evaluated to	Count	Threshold
Bin	True	8074	1

"if" / "when" / "else" condition on line 1559:

1559: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1560:

1560: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1562:

1562: elsif (sStallLogic = '0') then

	Evaluated to	Count	Threshold
Bin	True	98004	1

"if" / "when" / "else" condition on line 1576:

1576: if rising_edge(iClk) then

	Evaluated to	Count	Threshold
Bin	True	102207	1

"if" / "when" / "else" condition on line 1577:

1577: if (iRst = '1') then

	Evaluated to	Count	Threshold
Bin	True	278	1

"if" / "when" / "else" condition on line 1579:

1579: elsif (sValid = '1') then

	Evaluated to	Count	Threshold
Bin	True	85312	1

"if" / "when" / "else" condition on line 1547:

1547: oKeep(OUT_WIDTH / 8 - 1 - i) <= '1' when sFramerVBytes > i else

	Evaluated to	Count	Threshold
Bin	True	3394	1

Back to summary

Coverage report for file:

File: ../../Sources/openjls_top.vhd

Current File:

Details:

Uncovered statements:

Signal assignment statement on line 1034:

Signal assignment statement on line 1036:

Excluded statements:

Covered statements:

If statement on lines 473 to 487:

If statement on lines 474 to 486:

Signal assignment statement on line 475:

Signal assignment statement on line 476:

Signal assignment statement on line 477:

Signal assignment statement on line 479:

Signal assignment statement on line 480:

If statement on lines 481 to 485:

Signal assignment statement on line 482:

Signal assignment statement on line 484:

Signal assignment statement on line 494:

Signal assignment statement on line 499:

If statement on lines 506 to 507:

Signal assignment statement on line 506:

Signal assignment statement on line 507:

If statement on lines 508 to 509:

Signal assignment statement on line 508:

Signal assignment statement on line 509:

If statement on lines 510 to 511:

Signal assignment statement on line 510:

Signal assignment statement on line 511:

If statement on lines 512 to 513:

Signal assignment statement on line 512:

Signal assignment statement on line 513:

If statement on lines 514 to 515:

Signal assignment statement on line 514:

Signal assignment statement on line 515:

If statement on lines 516 to 517:

Signal assignment statement on line 516:

Signal assignment statement on line 517:

Signal assignment statement on line 519:

Signal assignment statement on line 520:

If statement on lines 538 to 588:

If statement on lines 539 to 587:

Signal assignment statement on line 540:

Signal assignment statement on line 541:

Variable assignment statement on line 543:

Variable assignment statement on line 544:

If statement on lines 548 to 562:

Assertion statement on lines 549 to 551:

Signal assignment statement on line 553:

Assertion statement on lines 555 to 557:

Signal assignment statement on line 559:

Signal assignment statement on line 561:

If statement on lines 564 to 578:

Assertion statement on lines 565 to 567:

Signal assignment statement on line 569:

Assertion statement on lines 571 to 573:

Signal assignment statement on line 575:

Signal assignment statement on line 577:

If statement on lines 580 to 586:

Signal assignment statement on line 581:

Signal assignment statement on line 582:

Signal assignment statement on line 584:

Signal assignment statement on line 585:

If statement on lines 651 to 692:

If statement on lines 652 to 691:

Signal assignment statement on line 653:

Signal assignment statement on line 654:

Signal assignment statement on line 655:

Signal assignment statement on line 656:

Signal assignment statement on line 657:

Signal assignment statement on line 658:

Signal assignment statement on line 659:

Signal assignment statement on line 660:

Signal assignment statement on line 661:

If statement on lines 663 to 669:

Variable assignment statement on line 664:

Variable assignment statement on line 666:

Variable assignment statement on line 668: