| Available Reports |
|---|
| Alert Report |
| Functional Coverage Report(s) |
| ScoreboardPkg_slv Report(s) |
| Link to Simulation Results |
| tb_openjls_axis_regs_osvvm.vhd |
| OSVVM_OpenJls Build Summary |
tb_openjls_axis_regs_osvvm Alert Report
tb_openjls_axis_regs_osvvm Alert Settings
| Setting | Value | Description | |
|---|---|---|---|
| FailOnWarning | true | If true, warnings are a test error | |
| FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
| FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
| External | Failures | 0 | Added to Alert Counts in determine total errors |
| Errors | 0 | ||
| Warnings | 0 | ||
| Expected | Failures | 0 | Subtracted from Alert Counts in determine total errors |
| Errors | 0 | ||
| Warnings | 0 | ||
tb_openjls_axis_regs_osvvm Alert Results
| Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
| tb_openjls_axis_regs_osvvm | PASSED | 161 | 161 | 0 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| Default | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Requirements | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OJLS.AxiLiteRegMap | PASSED | 17 | 17 | 0 | 16 | 17 | 0 | 0 | 0 | 0 | 0 | 0 |
| OJLS.AxiApplyReconfig | PASSED | 58 | 58 | 0 | 57 | 58 | 0 | 0 | 0 | 0 | 0 | 0 |
| OJLS.AxiAbortReencode | PASSED | 58 | 58 | 0 | 57 | 58 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_manager | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteResp SB | PASSED | 12 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadResp SB | PASSED | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_tx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| TxBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_rx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RxBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
tb_openjls_axis_regs_osvvm Coverage Report
Total Coverage: 100.00
Coverage Models with CovWeight = 0. Ignored in GetCov calculations. Used for OSVVM DelayCoverage.
WriteAddrDelayCov BurstLength Coverage Model Coverage: 0.0
WriteAddrDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 645950163, 1034705521 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddrDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddrDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteAddrDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1768436911, 1311413072 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddrDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddrDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteAddrDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 964875763, 1924412768 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddrDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstLength Coverage Model Coverage: 0.0
WriteDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 645950163, 241384789 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1768436911, 523158494 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 964875763, 1131092036 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteRespDelayCov BurstLength Coverage Model Coverage: 0.0
WriteRespDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 645950163, 1659921558 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteRespDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteRespDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteRespDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1768436911, 1941695263 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteRespDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteRespDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteRespDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 964875763, 402145406 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteRespDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadAddrDelayCov BurstLength Coverage Model Coverage: 0.0
ReadAddrDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1192126913, 1888307575 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddrDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddrDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadAddrDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1768436911, 401189957 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddrDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddrDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadAddrDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 745604884, 1783122134 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddrDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstLength Coverage Model Coverage: 0.0
ReadDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1192126913, 2056422920 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1768436911, 569305302 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadDataDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 745604884, 1956303633 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
DelayCov BurstLength Coverage Model Coverage: 0.0
DelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1551618641, 1873531553 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 3 to 11 | 0 | 80 | 0.0 | |
| COUNT | 109 to 131 | 0 | 20 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
DelayCov BurstDelay Coverage Model Coverage: 0.0
DelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1055197901, 705523959 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 8 | 0 | 80 | 0.0 | |
| COUNT | 108 to 156 | 0 | 20 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
DelayCov BeatDelay Coverage Model Coverage: 0.0
DelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1054477649, 865789184 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 85 | 0.0 | |
| COUNT | 1 | 0 | 10 | 0.0 | |
| COUNT | 2 | 0 | 5 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
DelayCov BurstLength Coverage Model Coverage: 0.0
DelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 455852208, 426451566 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 3 to 11 | 0 | 80 | 0.0 | |
| COUNT | 109 to 131 | 0 | 20 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
DelayCov BurstDelay Coverage Model Coverage: 0.0
DelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1739263641, 1705026400 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 2 to 8 | 0 | 65 | 0.0 | |
| COUNT | 0 | 108 to 156 | 0 | 10 | 0.0 | |
| COUNT | 1 | 2 to 8 | 0 | 15 | 0.0 | |
| COUNT | 1 | 108 to 156 | 0 | 10 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
DelayCov BeatDelay Coverage Model Coverage: 0.0
DelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1738543389, 768229425 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| IsRequirement | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 100 |
DelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 85 | 0.0 | |
| COUNT | 0 | 1 | 0 | 5 | 0.0 | |
| COUNT | 1 | 0 | 0 | 5 | 0.0 | |
| COUNT | 1 | 1 | 0 | 5 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
tb_openjls_axis_regs_osvvm Scoreboard Report for Scoreboard_slv
| Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
|---|---|---|---|---|---|---|---|
| WriteResp SB | u_manager | 12 | 0 | 12 | 12 | 0 | 0 |
| ReadResp SB | u_manager | 16 | 0 | 16 | 16 | 0 | 0 |
| WriteAddrFifo | u_manager | 12 | 0 | 0 | 12 | 0 | 0 |
| WriteDataFifo | u_manager | 12 | 0 | 0 | 12 | 0 | 0 |
| ReadAddrFifo | u_manager | 16 | 0 | 0 | 16 | 0 | 0 |
| ReadByteAddrFifo | u_manager | 16 | 0 | 0 | 16 | 0 | 0 |
| ReadDataFifo | u_manager | 16 | 0 | 0 | 16 | 0 | 0 |
| TransmitFifo | u_tx | 40 | 0 | 0 | 40 | 0 | 0 |
| ReceiveFifo | u_rx | 21 | 0 | 0 | 21 | 0 | 0 |
| TxBurstFifo | u_tx | 40 | 0 | 0 | 40 | 0 | 0 |
| RxBurstFifo | u_rx | 154 | 0 | 0 | 154 | 0 | 0 |